Silicon Power Devices: A New Chapter in Silicon Innovation

The planar 1D MOSFET, often exemplified by International Rectifier’s (IR) HEXFET™ technology, marked a significant advancement in silicon power semiconductors during the late 1970s and 1980s. Introduced by IR in 1979, the HEXFET was one of the first commercially successful power MOSFETs, featuring a unique hexagonal cell structure that optimized gate density and reduced R_DS(on) compared to earlier bipolar transistors. This design allowed for faster switching speeds, lower drive power requirements, and improved efficiency, making it ideal for applications like motor controls, power supplies, and automotive electronics.

At its core, the planar 1D MOSFET uses a vertical structure where the drift region is uniformly doped, and the gate is formed on the surface in a planar configuration. This allows 100% of the drift region to be dedicated to conduction, maximizing current-carrying capability without the need for compensating structures. The HEXFET’s hexagonal geometry further enhanced this by enabling tighter cell packing, which lowered R_DS(on) while maintaining high breakdown voltages (BV).

Over time, the technology evolved with key improvements, such as the introduction of trench gate architectures in the 1990s. Trench gates, where the gate electrode is etched into a vertical trench, created a vertical channel that further reduced R_DS(on) by shortening the channel length and improving electron mobility. This enhancement built on the planar foundation, allowing for even better performance in medium-voltage applications.

However, the planar 1D MOSFET has inherent limitations tied to silicon’s material properties. In these devices, the specific on-resistance (R_sp) increases with the breakdown voltage raised to the power of approximately 2.5 (R_sp ∝ BV^2.5), following the theoretical silicon limit for unipolar devices. This relationship arises because higher BV requires a thicker, lower-doped drift region to support the voltage, which in turn increases resistance.

As a result, planar 1D structures like the HEXFET were most effective for low-voltage applications (typically below 200 V) where R_DS(on) can remain competitively low. For higher voltages, the resistance becomes prohibitively high, leading to increased power losses and reduced efficiency, which prompted the development of more advanced architectures like Superjunction MOSFETs.

Building on the limitations of planar 1D MOSFETs, the RESURF (Reduced Surface Field) Superjunction MOSFET emerged as a transformative technology for high-voltage applications above 400 V. Patented in the early 1980s and commercialized by 1998, Superjunction devices employ a two-dimensional (2D) structure with alternating vertical p-type and n-type columns in the drift region. This design leverages charge compensation to achieve superior performance, allowing for higher doping levels in the n-columns to minimize R_DS(on) while preserving high breakdown voltage.

The key innovation lies in how the p-type columns reshape the electric field during off-state operation. In traditional planar devices, the electric field peaks sharply at the surface, forming a triangular profile that limits BV and necessitates thicker, lower-doped drift layers for higher voltages. Superjunction’s p-n junctions enable lateral depletion: as reverse bias is applied, the p-columns deplete the adjacent n-columns sideways, creating a more uniform, rectangular electric field distribution across the drift region. This flattening reduces peak field intensity, supports voltage blocking of 13-15 V/µm, and allows the device to handle higher BV without proportionally increasing resistance.

As a result, Superjunction MOSFETs break the silicon limit of planar structures, where R_sp scales with BV raised to the power of approximately 2.5 (R_sp ∝ BV^2.5). Instead, R_sp increases linearly with BV (R_sp ∝ BV), dramatically lowering losses in high-voltage scenarios like power supplies, EV chargers, and industrial drives. Today’s advanced Superjunction devices achieve R_DS(on) as low as 7 mΩ for 600 V.

Field plate technology has become a cornerstone for silicon power MOSFETs in medium- to low-voltage applications, particularly below 300 V, where Superjunction structures face challenges in achieving narrow p-type columns. This approach utilizes trench-based designs with polysilicon electrodes, insulated by thick oxide layers, embedded within the drift region. These field plates act as electrostatic shields, reshaping the electric field to create a uniform distribution through capacitive coupling, akin to the RESURF effect seen in Superjunctions, but without relying on p-n junctions for charge balance.

In the off-state, field plates laterally deplete the n-type drift region (mesa), enabling higher doping levels in the conduction path while maintaining BV. This reduces specific R_sp, with R_sp scaling approximately with BV^1.5-2, offering a significant improvement over planar 1D MOSFETs. The advanced “split-gate” configuration, where the gate and field plate are separated within the trench, further optimizes performance by minimizing gate-drain capacitance (Cgd), enhancing switching efficiency. State-of-the-art processes achieve mesa widths as low as 0.5 μm, yielding silicon efficiencies around 40% and R_DS(on) values below 5 mΩ for 100 V devices, making field plates highly effective for applications like DC-DC converters and battery management systems.

Future roadmaps focus on tightening mesa widths and increasing epitaxial doping to further reduce R_sp, maintaining field plate viability for low-voltage, high-efficiency applications. However, scaling challenges and performance trade-offs at higher voltages set the stage for alternative technologies to address broader voltage ranges.

Superjunction MOSFETs, while revolutionary for high-voltage applications, face significant manufacturing challenges that limit scalability and cost-effectiveness. Traditional fabrication relies on multi-epitaxial (multi-epi) growth, where the drift region is built layer by layer – typically 5-10 μm thick in lower-performance devices – requiring doping of alternating p- and n-type regions after each epi growth.
For a 55 μm stack supporting 600-650 V, this can necessitate 5-11 layers, resulting in wavy p-pillars due to diffusion and misalignment, as seen in cross-sections of coarser processes. Higher-performance variants employ finer epi steps (around 2-3 μm), enabling tighter charge balance and lower R_DS(on), but demand even more layers (up to 20+), additional mask steps, and stringent process control to minimize defects and maintain uniformity. These complexities increase fabrication costs, cycle times, and yield risks, constraining further density improvements without exponential rises in complexity.
Field plate technologies, effective for voltages below 300 V, encounter limitations as BV increases due to oxide thickness (tox) requirements. Field plates are tied to source so oxides must be included to block voltage in the structure. Tox scales proportionally with voltage to withstand electric fields, widening trenches and reducing silicon efficiency: from ~39% at 100 V (tox ≈600 Å) to ~9% at 300 V (tox ≈1500 Å). This forces larger cell pitches (e.g., from 2.55 μm to 4.2 μm between 100 V and 150 V), compromising R_DS(on) and scalability, especially above 100 V where manufacturing thick, uniform oxides becomes impractical.
Faced with these barriers in silicon-based architectures, and without ideas or invention for where to go next in silicon, the industry turned to wide bandgap semiconductors like SiC and GaN for breakthroughs in efficiency and power density, as customer demands for higher performance outpaced incremental silicon advancements.

Faced with these barriers in silicon-based architectures, and without ideas or invention for where to go next in silicon, the industry turned to wide bandgap semiconductors like SiC and GaN for breakthroughs in efficiency and power density, as customer demands for higher performance outpaced incremental silicon advancements.

Despite the challenges, silicon remains a crucial material in power electronics due to its inherent advantages:

Supply Chain

Silicon has a well-established and mature supply chain. Silicon is abundant and therefore low-cost. The infrastructure for manufacturing silicon devices is also extensive and, with foundries located across the world, is a secure supply chain.

This ensures a reliable and stable supply of silicon power devices. Supply chain stability in GaN and SiC is still maturing and can present challenges for some applications.

Cost

Silicon power devices are significantly less expensive than WBG devices. The mature manufacturing processes and high production volumes contribute to the lower cost of silicon devices. Total cost of ownership, including device cost, system-level costs, and long-term reliability, often favors silicon in many applications.

The cost of switching to GaN or SiC can be substantial, involving not only the higher device cost but also the cost of redesigning power electronic systems to accommodate the different characteristics of WBG devices. Complicated gate drive requirements, parasitic inductance limitations and electromagnetic interference are just a few challenges that must be overcome.

Market Share

Silicon remains the most commonly used substrate for power semiconductors.

In 2023, Grand View Research stated silicon’s market share in power electronics (by revenue) was 88.9%. It also cited that demand was increasing.

While few reports exist showing the share based on units shipped, the significantly lower cost than either SiC or GaN suggests silicon’s market share is considerably over 90%.

SuperQ™ technology marks a transformative leap in discrete silicon power design. It was announced in 2023 and released to production in 2025 to address the limitations of traditional architectures like Superjunction and field plates. This revolutionary approach employs an asymmetrical RESURF structure, achieving near-ideal charge balance with a thinner epitaxy layer. By optimizing the drift region’s n-type conduction area – with a roadmap to nearly doubling it compared to Superjunction devices – SuperQ significantly lowers on-resistance while maintaining high breakdown voltage. This results in industry leading resistance and switching losses.

Unlike Superjunction’s multi-epitaxial complexity or field plate’s oxide thickness constraints, SuperQ leverages a simplified process with wider n-type mesas (e.g., 75% silicon efficiency vs. 50% in Superjunction) and minimal trench requirements, avoiding thick oxide dependencies. This preserves silicon’s cost-effectiveness, availability, and reliability, aligning with the established manufacturing ecosystem. The technology’s scalability across 60 V to 1,200 V ranges positions it as a higher performance alternative to existing silicon while preserving the Cost x Performance ratio that design engineers have come to expect.